1. Field of Invention
This invention relates to the field of solid state devices for information storage and in particular for a method and structure to solve the problem of noise sensitivity and to reduce power consumption in reading the voltage stored on a bit cell in a random access memory.
2. Background of the Related Art
Dynamic random access memory, DRAM, is a type of random access memory that stores data in bit cells within an integrated circuit. A bit cell typically includes one capacitor as the storage mechanism. Broadly speaking the read process used in DRAM technology takes the analog voltage data stored in the bit cell, translates it into a standard digital logic voltage, makes this voltage available on a bit line and interprets the voltage as the digital binary value of 0 or 1.
The first widely used architecture for DRAM used a structure that included three transistors and accordingly was commonly referred to as “3T”. As technology advanced, an architecture was developed that included only one transistor to read the storage capacitor. This widely used “1T” architecture currently dominates the market. Both of these architectures have several well-known limitations and inherent drawbacks.
It has been a longstanding goal of the industry to reduce memory size. A significant reduction in size was accomplished by moving from the 3T architecture to the 1T architecture, but this change came with disadvantages. The 1T architecture needs a complicated sense amplifier and custom design work for each memory system design change. These needs increase design cycle time and manufacturing costs.
Another goal of the industry is to reduce read time. Any architecture that reduces read time is greatly desired.
Yet another longstanding goal of the industry is to reduce memory power consumption. The industry is continuously striving to reduce power consumption.
It has also been a longstanding goal of the industry to obtain increased memory capacity. One technique to increase memory capacity is to store multiple bits per storage mechanism. Neither the previously used 3T nor the more recent 1T architectures are functionally capable of meeting this need.
The 3T is limited to a single bit per storage mechanism by design. It utilizes a binary function, specifically either a voltage change or lack of voltage change on the read bit line, to indicate the value stored on the storage mechanism. The 1T is limited to a single bit per storage mechanism by functionality. It senses the voltage difference between two bit lines. This difference in voltage is small and read from a floating bit line thereby making it susceptible to noise. The noise factor makes it impractical to represent multiple bits per storage mechanism.
U.S. Pat. No. 5,841,695 to Wik (incorporated herein by reference) attempts to overcome the inherent binary limitations of the 3T by increasing the number of storage mechanisms in a bit cell from one storage mechanism to three. While the three storage mechanisms allow multi-bit storage within a single cell, the power consumption of such a system is similar to the combined power consumption of three single bit cells. Thus, practically speaking, there is no advantage.
U.S. Pat. No. 7,133,311 to Liu (incorporated herein by reference) discloses a method, based on a 1T architecture, of sensing three voltage levels representing 1.5 bits per storage mechanism however, it is limited to the noise sensitivity of the 1T architecture. In fact, U.S. Pat. No. 7,133,311 teaches away from the notion of using four levels, concluding that such arrangement would not be feasible due to increased noise.
These four goals, reduced memory size, reduced read time, reduced power consumption, and increased memory capacity constitute a long felt, ongoing and unmet need in the industry. It is desirable to develop a device and method that provides these advantages without any of the limitations of the prior art.